1. Field of the Invention
The present invention relates generally to a semiconductor storage device. More particularly, the invention relates to a semiconductor storage device which enables relieving by programming a column address of a defective cell in a redundancy judgment circuit when a defective memory cell is found during fabrication process.
2. Description of the Related Art
Conventionally, in the semiconductor storage device of this type is constructed with a column decoder 10, a redundancy column decoders 2 and 3, a row decoder 4, a memory cell array 20, an amplifier circuit 6, a redundancy judgment circuits 11 and 12, an internal clock generating circuit 31, a command decoder 32, an internal address generating circuit 33, a column system circuit 34, an input/output circuits 35 to 38 and a row system control signal generating circuit 39, as shown in FIG. 9.
The internal clock generating circuit 31 generates an internal clock ICLK on the basis of a reference clock CLK input externally. The command decoder 32 inputs /RAS, /CAS, /WE and /CS. The row system control signal generating circuit 39 receives a result of decoding from the command decoder 32 to generate a row system control signal.
The column system circuit 34 receives a result of decoding from the command decoder 32 to generate a column system control signal. An internal address generator circuit 33 is responsive to an external address input ADD and the result of decoding from the command decoder 32 to generate a row address and a column address in synchronism with the internal clock ICLK.
The row decoder 4 is responsive to the row system control signal and the row address to select one of a plurality of word lines WL depending upon the row address and also one of a plurality of a plate selection signals (not shown).
The redundancy judgment circuits 11 and 12 are responsive to the column address to make judgment whether the input column address is a preliminarily programmed redundancy address or not to output redundancy judgment signals R1 and R2.
The column decoder 10 is responsive to the column address and the redundancy judgment signals R1 and R2 not to select or select one of a plurality of column selection lines depending upon the column address. The redundancy column decoders 2 and 3 are responsive to the redundancy judgment signals R1 and R2 for determining whether the corresponding redundancy column selection line is to be selected or not.
The memory cell array 20 is connected to the word lines WL, the column selection lines, the redundancy selection line and an IO (input/output) line for receiving inputs therethrough. The input/output circuits 35 to 38 are connected one of input/output terminals DQ0 to DQ3 to read out data on read/write buses RWBUS0 to RWBUS3 or write data in the read/write buses RWBUS0 to RWBUS3 corresponding to output of the column system circuit 34 and whereby to perform reading and writing. The amplifier circuit 6 is connected to the column system circuit 34 to receive output therefrom and also to the I0 line and the read/write buses RWBUS0 to RWBUS3.
As shown in FIG. 10, the memory cell array 20 is constructed with a plurality of plates (plate 1, plate 2 . . . ). Each plate is connected to a plurality of word lines WL and a plurality of bit line pairs which are, in turn, connected to sense amplifiers (SA). Each column line and each redundancy column line are connected to four sense amplifiers per plate, respectively.
On the other hand, the sense amplifier SA receives a plate selection signal (plate selection signal 1, plate selection signal 2 . . . ) corresponding to each plate on the bit line pair connected thereto. Four sense amplifiers connected to the same column line or the same redundancy column selection line in each plate are connected to respectively different IO lines.
Four IO lines wired to each plate are connected to respectively corresponding IO lines of other plate output side of the memory cell array 20, and are also connected to the amplifier circuit 6. To the bit line pair and the work line WL, a plurality of memory cells are connected.
The redundancy column decoders 2 and 3 receives respective redundancy judgment signals R1 and R2, as shown in FIG. 11, and are constructed with buffer circuits (BUF) 2a and 3a driving one redundancy column selection line.
The column decoder 10 is constructed with an OR circuit 10a deriving an OR of the redundancy judgment signals R1 and R2, AND circuits 10b-1 to 10b-n deriving AND of an output of the OR circuit 10a and the column address. A plurality of column addresses input to respective AND circuits 10b-1 to 10b-n have different combination of high (High)/low (Low) per address so as to select only one column selection line.
Next, discussion will be given for operation of the conventional semiconductor storage device with reference to FIG. 12. The semiconductor storage device receives active command upon rising of the clock of cycle C1 (not shown) to select one of the word lines WL of row address corresponding to the data on the address terminal and one of the plate selection signals selecting the plate including the selected word line WL.
Subsequently, upon rising the clock of cycle C2, the read command is input and, at this time, if the data of the address terminal is a normal column address not preliminarily programmed in the redundancy judgment circuits 11 and 12, both of the redundancy judgment signals R1 and R2 are redundancy non-selected condition (low level), one column selection line corresponding to the data of the address terminal is selected (low level), and the redundancy selection line is not selected (low level).
Then, upon rising of the clock of the cycle C3, the semiconductor storage device receives the read command and if the data of the address terminals is the redundancy column address preliminarily programmed in the redundancy judgment circuit 11, the programmed redundancy judgment signal R1 output from the redundancy judgment circuit 11 becomes selected condition (high level), and all of the column selection lines becomes non-selected state (low level). Also, the redundancy selection line corresponding to the redundancy judgment signal R1 becomes selected condition (high level), and other redundancy column selection lines are not selected (low level).
Furthermore, upon rising of the clock of the cycle C4, the semiconductor storage device receives the read command and if the data of the address terminals is the redundancy column address preliminarily programmed in the redundancy judgment circuit 11, the programmed redundancy judgment signal R2 output from the redundancy judgment circuit 11 becomes selected condition (high level), and all of the column selection lines becomes non-selected state (low level). Also, the redundancy selection line corresponding to the redundancy judgment signal R2 becomes selected condition (high level), and other redundancy column selection lines are not selected (low level).
The column selection line corresponding to the programmed column address is not selected even when the corresponding address is input, and in place, the redundancy column selection line is selected. Therefore, the bit line and the sense amplifier connected to the defective cell are not used, and through the sense amplifier and bit line connected to the redundancy column selection line, the redundancy memory cell is selected.
Accordingly, even when defective memory cell is found during fabrication process of the semiconductor storage device, it can be relieved by programming the column address of the defective cell in the redundancy judgment circuits 11 and 12.
On the other hand, in each read command input cycle, data amplified by selected one of the sense amplifiers is transmitted to each IO line, and then, is input to the amplifier circuit 6. Data further amplified by the amplifier circuit 6 is transmitted to the input/output circuits 35 to 38 through the read/write buses RWBUS0 to RWBUS3, and then output to the input/output terminals DQ0 to DQ3 at a predetermined timing.
On the other hand, upon inputting of the write command, data input to the input/output terminals DQ0 to DQ3 is transmitted to the amplifier circuit 6 via the input/output circuits 35 to 38 and the read/write buses RWBUS0 to RWBUS3, and is written in selected one of the sense amplifiers via the IO line and subsequently written to the selected memory cell via connected bit line pair.
In the foregoing semiconductor storage device, even when the defective memory cell is found in the fabrication process, the storage device can be relieved by programming the column address of the defective cell in the redundancy judgment circuit. However, if defective cells are caused beyond a number of the redundancy selection lines connected to the redundancy judgment circuit, the foregoing measure will not work.